In contemporary digital design, the desired behavior is typically modeled using a Hardware Description Language (HDL). An HDL is characterized by a number of hardware-oriented features, such as support for massive concurrency, built-in determinism, and bit-level types. The most widely used HDLs are Verilog and VHDL.

MyHDL is a Python library that turns Python into an HDL. This has the tremendous advantage that it opens the Python ecosystem to hardware designers. MyHDL users directly benefit from Python's ease of use, descriptive power, and extensive libraries. Moreover, MyHDL brings modern techniques such as agile development to the hardware design world.

In this talk, the design of the MyHDL library will be explained. Topics include the modeling of concurrency using generators and decorators, and the type system. Moreover, a brief description of a number of industrial projects will illustrate the practical benefits of MyHDL.